Summer Internship & Training: VLSI Design Using CAD Tools (VLSI-CAD 2026)-NIT Rourkela

Program Schedule & Mode

• Dates: 18th May – 2nd July 2026
• Mode: OFFLINE (At NIT Rourkela Campus)
• Registration Deadline: 30th April 2026 (or until 50 seats are filled)

Program Modules

Module I: RTL Design, Simulation, and FPGA Prototyping

(18th May – 23rd May 2026)

Digital Logic Design & RTL using Verilog.

Functional Simulation, Synthesis, and Optimization.

FPGA Architecture, Implementation, and Debugging.

Module II: RTL-to-GDSII ASIC Design Flow

(25th May – 30th May 2026)

ASIC Design Methodology & Logic Synthesis.

Design for Testability (DFT).

Floor-planning, Placement, Routing, and Physical Verification (DRC & LVS).

Module III: Summer Internship

(01st June – 02nd July 2026)

Build and complete a real-world project in VLSI, Embedded Systems, & IoT.

Tools Covered

Gain hands-on experience with industry-standard tools:

Synopsys

Cadence

AMD Xilinx Vivado

Eligibility & Seats

• Who Can Apply: BTech, MTech, PhD students (EC/EE/CS), Faculty, Industry Professionals, and R&D Researchers.
• Prerequisite: Basic knowledge of Digital Electronics is mandatory.
• Seat Limit: Only 50 seats available (First-Come, First-Serve basis).

Certification

Certificates for both STCs and the summer internship will be awarded to students who successfully complete the training and internship in offline mode.

Registration & Contact

• Coordinator: Prof. A. K. Swain
• Mobile: +91 94373 41298
• Email: vlsi.nitrk@gmail.com
• Location: Dept. of Electronics and Communication Engineering, NIT Rourkela - 769008.

Secure your spot in this high-demand program before the April 30th deadline!

Dates: 18th May – 2nd July 2026

Mode: OFFLINE (At NIT Rourkela Campus)

Registration Deadline: 30th April 2026 (or until 50 seats are filled)

Prerequisite: Basic knowledge of Digital Electronics is mandatory.

Seat Limit: Only 50 seats available (First-Come, First-Serve basis).